At this moment I have a very simple testbench to test the filter. I created a short test vector which checks calculations in the filter, but in very narrow range and only for 10 input samples. It really does not check much at all.
Below is depicted an actual method of testing:
It contains only an UUT, a short input vector, and output data which must be checked manually. Not much. Can I be sure that UUT will be tested in all corners? No.
What is more, that simple testbench has many disadvantages. If I change width of the data or want to add or remove some data I will have to redesign it. This is not flexible solution and is difficult in use.
I wanted to show another way of testing, which removes all mentioned disadvantages. In complex VHDL projects where a test vector contains thousands of samples I use files to store in/out data.
What is advantage of that solution? I can create a file with data in an application which is dedicated for it. I can very easily create many different vectors. I can change length or width of the vector. This approach extends ways of generating input vectors and allows to put there anything I want…
Now two new things have to be explained. First, what kind of software use to create vectors, and the second, how can I check if output data is correct, when input vector contains thousands of samples?
Next draw should solve all these doubts:
I use software for numerical computations like Matlab, Octave or any other. That kind of software allows to generate input data and create a model of tested unit. Generated files should be standard text-plain files. After generating test vectors I can send them through the model of the filter. At output I should get reference data, which later can be used to verify if the VHDL model works properly and gives the same results.
Then I have to do exactly the same with the VHDL model. The testbench should read data from the file and write the results to another one. After all tests, two output files should be compared.
What do I need to do to achieve those goals in my example?
- create model of the filter in Matlab
- generate input data in Maltab and write it to a file
- write output data from Matlab to a file
- write blocks in VHDL which will be able to read data from a file and write to another one
- create top testbench which will connect all that new modules.
VHDL Guide 