This is the last part about creating almost automatic testbench for Moving Average Filter. In the previous post I presented blocks for reading and writing. Now it is time to connect all blocks to each other in the main testbench. Testbench contains three blocks:
Testbench additionally contains clock generation and other processes which drive control and testbench signals.
At this moment I have a very simple testbench to test the filter. I created a short test vector which checks calculations in the filter, but in very narrow range and only for 10 input samples. It really does not check much at all.
Below is depicted an actual method of testing:
In previous posts I specified how filter should work and I described it in VHDL. Now it came time to test our filter. Below you can find very basic testbench:
Wait is very useful operation for simulation. It easily allows to simulate timing or signal dependencies. In next posts I am going to use it more often, so I wanted to give a short information about that statement.
Having entity declaration and body architecture only one thing is still to do before compilation. I have to inform compiler which libraries are needed to analyze the design. Therefore, before entity declaration I inserted name of the library and package which will be used. This is ieee library and package std_logic_1164 (package, which contains declarations of basic types used in the design).
VHDL Guide 