Array – basics

Array, a collection of values of the same type, is very useful representation of data in VHDL. It is helpful during creating memory blocks (FIFOs, shift registers, RAM, ROM) or in designs where exist duplicated data flows, pipes or blocks (many ADC channels, filters etc).  They can be used in synchronous designs as well as in combinational. But using it in combinational parts, sometimes for specific solution, it is very important to be aware how the code will be interpreted and synthesized.

To use the array object in the code, we need to do following steps:

1. declare a new type
2. declare signal of a new type
3. use it properly in the code

Attribute LENGTH

I don’t like magic numbers or redundant variables in the code. They make it unclear and unreadable. Fortunately, VHDL gives many various options to eliminate such parts. One of them are predefined attributes. VHDL delivers many groups of attributes, which are useful in many situations. Some of them work only with signals, other with specific data types etc., but in general, rule of using an attribute is always the same:

 object'attribute

Files – data representation mismatch

In previous post I explained in 5 steps how looks communication with files in VHDL. I presented some basic codes, which do simple write/read operations. Today I wanted to focus on that codes. If anyone tried to simulate them probably noticed that result are different from expectations. Below hopefully you will find an answer why…

Files – theory & examples

VHDL provides mechanism to work with files. This feature is useful, when there is a need to store some data like test vectors, parameters or results of the simulation. Way of working with files in VHDL is very similar to other languages. File is treated as an object.  It can be created in an architecture body, process or subprograms. To properly work with files, following steps should be done:

1. Define type of a file
2. Declare object of the defined file type
3. Open the file
4. Perform write/read operations
5. Close the file

Wait

Wait is very useful operation for simulation. It easily allows to simulate timing or signal dependencies. In next posts I am going to use it more often, so I wanted to give a short information about that statement.

Component

If you have a hierarchical design (so one block is built from others), you will have to instantiate and connect modules. Even if you have only one module and testbench dedicated for it, you will have to do that. In testbench used in previous post, I showed, how to instantiate a component, but there are more simpler ways to do that. Below you can find a few methods .

Generic

Generic is a basic and very useful function of the VHDL. It allows creating more flexible and easy to modify components. You should start using them right now. Proper use of them will save your time and make your code clearer and more readable.

Registers (synchronous designs)

In previous posts I showed, how to build OR gate. This was an example of combinational logic. If you look at the code, you will see, that output depends only on present inputs and changes as fast as possible after modifying them. Though you have to know how to build combinational logic and how it works,  you won’t create any bigger design only with that. To store data or pipeline the calculations, you have to create synchronous logic, dependent on a clock.

Architecture body

In previous post I presented entity declaration and gave simple example. Now it is time for second part – architecture body. Without this part, you won’t be able to create any module in VHDL.

Entity declaration gives information how module is connected with external world. Architecture body gives information what is inside of the module. It specifies relationship between input and output ports. In other words it specifies behavior of the module.

You should know there are three different modeling styles which allow to describe architecture body:

• structural description
• behavioral description
• dataflow description

Sometimes some people add the fourth style – mixed, which is combination of three mentioned styles.

Entity declaration

As mentioned in previous post, systems are created using one or more entities. In case of many entities in the project, the uppermost level of it, is top-level entity. To connect modules with other modules or external world, ports and signals are used (Fig. 1). Main role of entity declaration is to define these ports – their names, types, width and direction. Basically entity declaration shows how module is seen by other modules. It describes the external view of the module with no information what is inside. Additionally entity declaration includes name of the entity and other parameters (constants, types, asserts, function etc).