Array – basics

Array, a collection of values of the same type, is very useful representation of data in VHDL. It is helpful during creating memory blocks (FIFOs, shift registers, RAM, ROM) or in designs where exist duplicated data flows, pipes or blocks (many ADC channels, filters etc).  They can be used in synchronous designs as well as in combinational. But using it in combinational parts, sometimes for specific solution, it is very important to be aware how the code will be interpreted and synthesized.

To use the array object in the code, we need to do following steps:

1. declare a new type
2. declare signal of a new type
3. use it properly in the code

Attribute LENGTH

I don’t like magic numbers or redundant variables in the code. They make it unclear and unreadable. Fortunately, VHDL gives many various options to eliminate such parts. One of them are predefined attributes. VHDL delivers many groups of attributes, which are useful in many situations. Some of them work only with signals, other with specific data types etc., but in general, rule of using an attribute is always the same:

 object'attribute

Developing design: moving average filter. Part 7 (last) – testbench.

This is the last part about creating almost automatic testbench for Moving Average Filter. In the previous post I presented blocks for reading and writing. Now it is time to connect all blocks to each other in the main testbench. Testbench contains three blocks:

• block which reads data from external file,
• filter,
• block which writes output data to external file.

Testbench additionally contains clock generation and other processes which drive control and testbench signals.

Developing design: moving average filter. Part 6 – reading and writing to the files.

I had a break in developing filter (last part is here), but before doing next steps, I had to make a short introduction to working with files in VHDL. You can read about it here, here and here. Now I am going to use that knowledge and move on with the filter. In the last part I implemented the filter in Octave, generated test vectors, sent them through the filter and wrote all data to files.

Now it is time to start building testbench, where the filter could be easily and automatically verified with different test vectors. To achieve it, testbench has to read data from a file and pass it to the filter and then, write output values from the filter to another file.

TextIO

Before you read that post, I encourage you to go through my two previous posts (here and here), which are about working with files. They describe basic approach and explain why that method is not recommended. Instead of this, in the following post I am proposing more standard, popular and convenient way to work with files in the VHDL.

TextIO is a package created to simplify working with files. It works in the same way on every operating system with almost every type available in the VHDL.

Files – data representation mismatch

In previous post I explained in 5 steps how looks communication with files in VHDL. I presented some basic codes, which do simple write/read operations. Today I wanted to focus on that codes. If anyone tried to simulate them probably noticed that result are different from expectations. Below hopefully you will find an answer why…

Files – theory & examples

VHDL provides mechanism to work with files. This feature is useful, when there is a need to store some data like test vectors, parameters or results of the simulation. Way of working with files in VHDL is very similar to other languages. File is treated as an object.  It can be created in an architecture body, process or subprograms. To properly work with files, following steps should be done:

1. Define type of a file
2. Declare object of the defined file type
3. Open the file
4. Perform write/read operations
5. Close the file

Developing design: moving average filter. Part 5 – model of the filter.

Next step in extending test automation is to create model of the filter and run some tests on it. Perfect applications which will do that job are environments for technical and mathematical computations like Matlab or Octave, which very easily allow to express even complex algorithms.

Developing design: moving average filter. Part 4 – automatization of tests – idea.

At this moment I have a very simple testbench to test the filter. I created a short test vector which checks calculations in the filter, but in very narrow range and only for 10 input samples. It really does not check much at all.

Below is depicted an actual method of testing:

Developing design: moving average filter. Part 3 – testbench.

In previous posts I specified how filter should work and I described it in VHDL. Now it came time to test our filter. Below you can find very basic testbench: